View MTD3302_8284560.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2000 september, 2004 ? rev. xxx 1 publication order number: MTD3302/d MTD3302 advance information power mosfet 18 amps, 30 volts n?channel dpak this power mosfet is capable of withstanding high energy in the avalanche and commutation modes and the drain?to?source diode has a very low reverse recovery time. these devices are designed for use in low voltage, high speed switching applications where power efficiency is important. typical applications are dc?dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. they can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. the avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. ? characterized over a wide range of power ratings ? ultralow r ds(on) provides higher efficiency and extends battery life in portable applications ? logic level gate drive ? can be driven by logic ics ? diode is characterized for use in bridge circuits ? diode exhibits high speed, with soft recovery ? i dss specified at elevated temperature ? avalanche energy specified maximum ratings (t j = 25 c unless otherwise specified) parameter symbol value unit drain?to?source voltage v dss 30 vdc drain?to?gate voltage v dgr 30 vdc gate?to?source voltage v gs 20 vdc gate?to?source operating voltage v gs 16 vdc operating and storage temperature range t j , t stg ?55 to 150 c single pulse drain?to?source avalanche energy ? starting t j = 25 c (v dd = 25 vdc, v gs = 10 vdc, l = 20 mh, i l(pk) = 10 a, v ds = 30 vdc) e as 1000 mj this document contains information on a new product. specifications and information herein are subject to change without notice. pin assignment 1 gate 3 source 2 drain 4 drain 18 amperes 30 volts r ds(on) = 10 m w device package shipping ordering information MTD3302 dpak 75 units/rail case 369a dpak style 2 http://onsemi.com n?channel d s g marking diagram y = year ww = work week t = mosfet yww t 3302 MTD3302t4 dpak 2500 tape & reel 1 2 3 4
MTD3302 http://onsemi.com 2 power ratings (t j = 25 c unless otherwise specified) parameter symbol value unit drain current ? continuous @ t a = 25 c drain current ? continuous @ t a = 100 c drain current ? single pulse (tp 10 s) mounted on heat sink t case = 25 c i d i d i dm 30 30 90 adc adc adc total power dissipation @ t a = 25 c linear derating factor case v gs = 10 vdc p d 96 769 watts mw/ c thermal resistance ? junction?to?case stead y state r q jc 1.3 c/w continuous source current (diode conduction) steady state i s 30 adc parameter symbol value unit drain current ? continuous @ t a = 25 c drain current ? continuous @ t a = 100 c drain current ? single pulse (tp 10 s) mounted on 1 inch square fr?4 or g10 board i d i d i dm 18.3 11.2 60 adc adc adc total power dissipation @ t a = 25 c linear derating factor v gs = 10 vdc p d 5.0 40 watts mw/ c thermal resistance ? junction?to?ambient t 10 seconds r q ja 25 c/w continuous source current (diode conduction) t ? ??????? ? ? M? ??? parameter symbol value unit drain current ? continuous @ t a = 25 c drain current ? continuous @ t a = 100 c drain current ? single pulse (tp 10 s) mounted on 1 inch square fr?4 or g10 board i d i d i dm 11.2 8.6 40 adc adc adc total power dissipation @ t a = 25 c linear derating factor v gs = 10 vdc p d 1.9 15 watts mw/ c thermal resistance ? junction?to?ambient stead y state r q ja 67 c/w continuous source current (diode conduction) steady state i s 2.5 adc parameter symbol value unit drain current ? continuous @ t a = 25 c drain current ? continuous @ t a = 100 c drain current ? single pulse (tp 10 s) mounted on minimum recommended fr?4 or g10 board i d i d i dm 8.3 5.2 30 adc adc adc total power dissipation @ t a = 25 c linear derating factor v gs = 10 vdc p d 1.0 8.3 watts mw/ c thermal resistance ? junction?to?ambient stead y state r q ja 120 c/w continuous source current (diode conduction) steady state i s 1.4 adc
MTD3302 http://onsemi.com 3 electrical characteristics (t j = 25 c unless otherwise specified) characteristic symbol min typ max unit off characteristics drain?to?source breakdown voltage (v gs = 0 vdc, i d = 250 adc) temperature coefficient (positive) v (br)dss 30 ? 33 23 ? ? vdc mv/ c zero gate voltage drain current (v ds = 30 vdc, v gs = 0 vdc) (v ds = 30 vdc, v gs = 0 vdc, t j = 125 c) i dss ? ? 0.005 0.5 1.0 10 m adc gate?body leakage current (v gs = 20 vdc, v ds = 0 vdc) i gss ? 2 100 nadc on characteristics (note 1.) gate threshold voltage (v ds = v gs , i d = 250 adc) threshold temperature coefficient (negative) v gs(th) 1.0 ? 1.9 4.6 ? ? vdc mv/ c static drain?to?source on?resistance (v gs = 10 vdc, i d = 10 adc) (v gs = 4.5 vdc, i d = 5.0 adc) r ds(on) ? ? 8.9 13 10 16 m w forward transconductance (v ds = 15 vdc, i d = 10 adc) g fs 12 19 ? mhos dynamic characteristics input capacitance (v 24 vd v 0vd c iss ? 1760 ? pf output capacitance (v ds = 24 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss ? 610 ? transfer capacitance f = 1 . 0 mhz) c rss ? 185 ? switching characteristics (note 2.) turn?on delay time t d(on) ? 10 20 ns rise time (v dd = 25 vdc, i d = 1.0 adc, v gs =10vdc t r ? 30 60 turn?off delay time v gs = 10 vdc, r g = 6.0 w ) t d(off) ? 65 130 fall time r g 6.0 w ) t f ? 58 110 turn?on delay time t d(on) ? 20 40 ns rise time (v dd = 25 vdc, i d = 1.0 adc, v gs =45vdc t r ? 86 170 turn?off delay time v gs = 4.5 vdc, r g = 6.0 w ) t d(off) ? 44 80 fall time r g 6.0 w ) t f ? 48 90 gate charge q t ? 47 60 nc (v ds = 15 vdc, i d = 2.0 adc, q 1 ? 4.8 ? (v ds 15 vdc , i d 2 . 0 adc , v gs = 10 vdc) q 2 ? 16.7 ? q 3 ? 11.2 ? source?drain diode characteristics forward on?voltage (note 1.) (i s = 2.3 adc, v gs = 0 vdc) (i s = 2.3 adc, v gs = 0 vdc, t j = 125 c) v sd ? ? 0.87 0.72 1.1 ? vdc reverse recovery time t rr ? 41 ? ns (i s = 2.3 adc, v gs = 0 vdc, t a ? 21 ? (i s 2 . 3 adc , v gs 0 vdc , di s /dt = 100 a/ m s) t b ? 20 ? reverse recovery stored charge q rr ? 0.047 ? m c 1. pulse test: pulse width 300 m s, duty cycle 2%. 2. switching characteristics are independent of operating junction temperatures.
MTD3302 http://onsemi.com 4 typical electrical characteristics r ds(on) , drain-to-source resistance (normalized) r ds(on) , drain-to-source resistance (ohms) 0 10 20 60 v ds , drain-to-source voltage (volts) figure 1. on?region characteristics i d , drain current (amps) 26 0 20 50 i d , drain current (amps) v gs , gate-to-source voltage (volts) figure 2. transfer characteristics 3 24 10 0 0.2 0.3 01020 60 0.020 v gs , gate-to-source voltage (volts) figure 3. on?resistance versus gate?to?source voltage i d , drain current (amps) figure 4. on?resistance versus drain current and gate voltage 1.5 2.0 51015 30 1 100 1000 t j , junction temperature ( c) figure 5. on?resistance variation with temperature v ds , drain-to-source voltage (volts) figure 6. drain?to?source leakage current versus voltage i dss , leakage (na) v ds 10 v t j = 125 c -55 c t j = 25 c v gs = 0 v i d = 5.0 a t j = 25 c v gs = 4.5 v v gs = 10 v i d = 10 a 3 3.5 68 10 v -50 -25 0 25 50 75 100 125 150 t j = 125 c 1.0 10 20 25 100 c r ds(on) , drain-to-source resistance (ohms) 0 0.25 0.5 1.25 1 1.5 2 30 10 40 60 0.002 0.004 0 0.5 0 0.1 0.1 30 25 c 0.75 1.75 t j = 25 c 6.0 v 2.5 30 25 c 57 9 40 0.006 0.008 0.010 0.012 0.014 0.016 0.018 4.3 v 4.1 v 3.9 v v gs = 10 v 3.5 v 3.3 v 3.1 v 40 50 3.7 v 4.5 v 4 4.5 5 5.5 50
MTD3302 http://onsemi.com 5 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain?gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn?on and turn?off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off?state condition when calculating t d(on) and is read at a voltage corresponding to the on?state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. gate-to-source or drain-to-source voltage (volts) c, capacitance (pf) 1000 4500 figure 7. capacitance variation 30 -10 0 5 10 -5 t j = 25 c c iss c oss c rss 15 20 25 0 2000 3000 c iss c rss v ds = 0 v v gs = 0 v v ds v gs 1500 2500 3500 500 4000
MTD3302 http://onsemi.com 6 figure 8. gate?to?source and drain?to?source voltage versus total charge r g , gate resistance (ohms) 1 10 100 100 10 t, time (ns) t r t d(on) figure 9. resistive switching time variation versus gate resistance 18 v gs , gate-to-source voltage (volts) 3 0 0 2 0 q g , total gate charge (nc) v ds , drain-to-source voltage (volts) 12 10 20 40 t j = 25 c i d = 30 a 30 v ds v gs qt q2 q3 q1 50 1000 t f t d(off) 8 6 9 12 4 10 6 15 t j = 25 c i d = 1.0 a v dd = 25 v v gs = 10 v drain?to?source diode characteristics the switching characteristics of a mosfet body diode are very important in systems using it as a freewheeling or commutating diode. of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, emi and rfi. system switching losses are largely due to the nature of the body diode itself. the body diode is a minority carrier device, therefore it has a finite reverse recovery time, t rr , due to the storage of minority carrier charge, q rr , as shown in the typical reverse recovery wave form of figure 11. it is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. therefore, one would like a diode with short t rr and low q rr specifications to minimize these losses. the abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. the mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. the diode's negative di/dt during t a is directly controlled by the device clearing the stored charge. however, the positive di/dt during t b is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. therefore, when comparing diodes, the ratio of t b /t a serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. a ratio of 1 is considered ideal and values less than 0.5 are considered snappy. compared to on semiconductor standard cell density low voltage mosfets, high cell density mosfet diodes are faster (shorter t rr ), have less stored charge and a softer reverse recovery characteristic. the softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell mosfet diode without increasing the current ringing or the noise generated. in addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. 0.5 0.55 0.6 0.65 0.7 0 5 10 v sd , source-to-drain voltage (volts) figure 10. diode forward voltage versus current i s , source current (amps) 0.75 0.9 30 v gs = 0 v t j = 25 c 15 20 25 0.8 0.85
MTD3302 http://onsemi.com 7 i s , source current t, time figure 11. reverse recovery time (t rr ) di/dt = 300 a/ m s standard cell density high cell density t b t rr t a t rr safe operating area the forward biased safe operating area curves define the maximum simultaneous drain?to?source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance ? general data and its use.o switching between the off?state and the on?state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded, and that the transition time (t r , t f ) does not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r q jc ). a power mosfet designated e?fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases non?linearly with an increase of peak current in avalanche and peak junction temperature. figure 12. maximum rated forward biased safe operating area 0.1 v ds , drain-to-source voltage (volts) 1 i d , drain current (amps) r ds(on) limit thermal limit package limit 10 dc 1 100 100 figure 13. maximum avalanche energy versus starting junction temperature 25 t j , starting junction temperature ( c) 200 400 e as , single pulse drain-to-source 75 0 50 1000 150 100 125 600 800 avalanche energy (mj) 10 10 ms 1 ms 100 s i d = 10 a 100 300 900 500 700 v gs = 10 v single pulse t c = 25 c
MTD3302 http://onsemi.com 8 typical electrical characteristics r q ja (t) = r(t) r q ja d curves apply for power pulse train shown read time at t 1 t j(pk) - t a = p (pk) r q ja (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 figure 14. thermal response ? various duty cycles t, time (seconds) rthja(t), effective transient thermal resistance 1000 1 d = 0.5 1e-05 1e-03 1e-02 1e-01 0.2 0.01 0.01 0.02 0.05 0.1 1e+00 1e+01 1e+03 single pulse figure 15. thermal response ? various mounting/measurement conditions 1e-04 1e+02 mounted to minimum recommended footprint power (w) 0.01 10 0 100 200 t, time (seconds) figure 16. single pulse power 1 50 0.1 di/dt t rr t a t p i s 0.25 i s time i s t b figure 17. diode reverse recovery waveform 150 mounted on 2 sq. fr4 board (1 sq. 2 oz. cu 0.06 thick single sided) t, time (seconds) rthja(t), effective transient thermal resistance 10,000 100 10 1e-04 1e-02 1e-01 1e+00 1e+01 1e+02 1e+03 0.1 1000 r thja , 1 inch pad r thjc, t case = 25 c chip junction r1 c1 r2 c2 r3 c3 r4 c4 r5 c5 ambient 1 2 3 4 5 0.0260 0.384 25.0 74.1 17.9 2.30 36.2 1521 5000 85,400 0.0256 0.314 5.07 19.6 41.7 0.753 9.97 230 1300 7,500 0.0324 0.0487 0.0896 0.464 0.666 0.0002 0.0006 0.0014 0.0073 0.0482 rc min pad, ja rc 1 inch pad, ja rc case mount, jc r thja , min pad duty cycle 100 10 0.1 1 1e-03 1e-05
MTD3302 http://onsemi.com 9 information for using the dpak surface mount package recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.190 4.826 mm inches 0.100 2.54 0.063 1.6 0.165 4.191 0.118 3.0 0.243 6.172 power dissipation for a surface mount device the power dissipation for a surface mount device is a function of the drain pad size. these can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. power dissipation for a surface mount device is determined by t j(max) , the maximum rated junction temperature of the die, r q ja , the thermal resistance from the device junction to ambient, and the operating temperature, t a . using the values provided on the data sheet, p d can be calculated as follows: p d = t j(max) ? t a r q ja the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device. for a dpak device, p d is calculated as follows. p d = 150 c ? 25 c 71.4 c/w = 1.75 watts the 71.4 c/w for the dpak package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 watts. note that these values may vary depending on the device type. consult the maximum ratings table on the data sheet to find the actual p d and r ja values for a particular device. there are other alternatives to achieving higher power dissipation from the surface mount packages. one is to increase the area of the drain pad. by increasing the area of the drain pad, the power dissipation can be increased. although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. for example, a graph of r q ja versus drain pad area is shown in figure 18. figure 18. thermal resistance versus drain pad area for the dpak package (typical) 1.75 watts board material = 0.0625 g-10/fr-4, 2 oz copper 80 100 60 40 20 10 8 6 4 2 0 3.0 watts 5.0 watts t a = 25 c a, area (square inches) to ambient ( c/w) r ja , thermal resistance, junction q
MTD3302 http://onsemi.com 10 another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad . using a board material such as thermal clad, an aluminum core board, the power dissipation can be doubled using the same footprint. solder stencil guidelines prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. solder stencils are used to screen the optimum amount. these stencils are typically 0.008 inches thick and may be made of brass or stainless steel. for packages such as the sc?59, sc?70/sot?323, sod?123, sot?23, sot?143, sot?223, so?8, so?14, so?16, and smb/smc diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. this is not the case with the dpak and d 2 pak packages. if one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or atombstoningo may occur due to an excess of solder. for these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. the opening for the leads is still a 1:1 registration. figure 16 shows a typical stencil for the dpak and d 2 pak packages. the pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. ?? ?? ?? ?? ??? ??? ??? ??? ??? ??? ??? ??? ?? ?? figure 19. typical stencil for dpak and d 2 pak packages solder paste openings stencil soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * due to shadowing and the inability to set the wave height to incorporate other surface mount components, the d 2 pak is not recommended for wave soldering.
MTD3302 http://onsemi.com 11 typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 20 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems, but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177 ?189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 arampo step 2 vent asoako step 3 heating zones 2 & 5 arampo step 4 heating zones 3 & 6 asoako step 5 heating zones 4 & 7 aspikeo step 6 vent step 7 cooling 200 c 150 c 100 c 5 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies desired curve for high mass assemblies 100 c 150 c 160 c 170 c 140 c figure 20. typical solder heating profile
MTD3302 http://onsemi.com 12 package dimensions style 2: pin 1. gate 2. drain 3. source 4. drain d a k b r v s f l g 2 pl m 0.13 (0.005) t e c u j h ?t? seating plane z dim min max min max millimeters inches a 0.235 0.250 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.033 0.040 0.84 1.01 f 0.037 0.047 0.94 1.19 g 0.180 bsc 4.58 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.090 bsc 2.29 bsc r 0.175 0.215 4.45 5.46 s 0.020 0.050 0.51 1.27 u 0.020 --- 0.51 --- v 0.030 0.050 0.77 1.27 z 0.138 --- 3.51 --- notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 123 4 dpak case 369a?13 issue aa on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 303?308?7143 (mon?fri 8:00am to 5:00pm mst) email : onlit?spanish@hibbertco.com toll?free from mexico: dial 01?800?288?2872 for access ? then dial 866?297?9322 asia/pacific : ldc for on semiconductor ? asia support phone : 303?675?2121 (tue?fri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 001?800?4422?3781 email : onlit?asia@hibbertco.com japan : on semiconductor, japan customer focus center 4?32?1 nishi?gotanda, shinagawa?ku, tokyo, japan 141?0031 phone : 81?3?5740?2700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. MTD3302/d thermal clad is a registered trademark of the bergquist company. north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : onlit@hibbertco.com fax response line: 303?675?2167 or 800?344?3810 toll free usa/canada n. american technical support : 800?282?9855 toll free usa/canada europe: ldc for on semiconductor ? european support german phone : (+1) 303?308?7140 (mon?fri 2:30pm to 7:00pm cet) email : onlit?german@hibbertco.com french phone : (+1) 303?308?7141 (mon?fri 2:00pm to 7:00pm cet) email : onlit?french@hibbertco.com english phone : (+1) 303?308?7142 (mon?fri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european toll?free access*: 00?800?4422?3781 *available from germany, france, italy, uk, ireland

▲Up To Search▲

Price & Availability of MTD3302

	To Download MTD3302 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .